190-MHz CMOS 4-Kbyte Pipelined Caches
نویسندگان
چکیده
In this paper we describe the design and implementation of a 190-MHz pipelined 4-Kbyte instruction and data cache. The caches are designed in 1.0-μm CMOS and measure 0.78 x 0.47 cm2. This paper describes the microarchitecture, cache timing, circuit implementation, and layout of both the instruction and the data cache. The key features of these caches are pipelined execution and the use of dynamic single-phase clock logic. We discuss the interface of this cache with the processor core and the off-chip controller. This paper also describes the pipelined structure of the cache and the miss detection and handling logic.
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